CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 525

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.2.4
Read: Anytime
Write: Has no effect
Freescale Semiconductor
Reset
SPTEF
MODF
Field
SPIF
7
5
4
W
R
SPIF
SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register.
This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data
register.
0 Transfer not yet complete.
1 New data copied to SPIDR.
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear
this bit and place data into the transmit data register, SPISR must be read with SPTEF = 1, followed by a write
to SPIDR. Any write to the SPI data register without reading SPTEF = 1, is effectively ignored.
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 12.3.2.2, “SPI Control Register 2
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
SPI Status Register (SPISR)
0
7
= Unimplemented or Reserved
0
0
6
Figure 12-6. SPI Status Register (SPISR)
Table 12-7. SPISR Field Descriptions
SPTEF
MC9S12XDP512 Data Sheet, Rev. 2.21
1
5
(SPICR2)”. The flag is cleared automatically by a read of the SPI status
MODF
0
4
Description
0
0
3
Chapter 12 Serial Peripheral Interface (S12SPIV4)
0
0
2
0
0
1
0
0
0
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