CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 685

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any

PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in

emulation modes.

A summary of PRR accesses:

Freescale Semiconductor

An aligned word access to a PRR will take 2 bus cycles.

A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the

misaligned word access is not a PRR, the access will take only 3 cycles.

A byte access to a PRR will take 2 cycles.

MC9S12XDP512 Data Sheet, Rev. 2.21

Table 18-23. PRR Listing

PRR Local Address

Chapter 18 Memory Mapping Control (S12XMMCV3)

PRR Location