CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 792

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21 External Bus Interface (S12XEBIV2)
21.4
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
21.4.1
A summary of the external bus interface functions for each operating mode is shown in
1
2
3
4
794
Data direction signals
threshold enabled on
unimplemented area
Incl. S12X_EBI registers
Refer to S12X_MMC section.
If EWAITE = 1, the minimum number of external bus cycles is 3.
Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
Data select signals
(if 16-bit data bus)
address access
visible externally
address access
Internal access
Reduced input
PRR access
External wait
(if Enabled)
Bus signals
Properties
Flash area
External
access
feature
and
Functional Description
Operating Modes and External Bus Properties
2
1
4
write internal
Single-Chip
read internal
2 cycles
Normal
Single-Chip Modes
—
—
—
—
—
—
—
—
Table 21-7. Summary of Functions
MC9S12XDP512 Data Sheet, Rev. 2.21
write internal
Single-Chip
read internal
2 cycles
Special
—
—
—
—
—
—
—
—
Timing Properties
Signal Properties
Max. of 2 to 9
or n cycles of
write internal
programmed
read internal
ADDR[22:1]
DATA[15:0]
Expanded
Table 21-3
ext. wait
2 cycles
Normal
Refer to
EWAIT
cycles
UDS
LDS
WE
RE
—
—
3
ADDR[22:20]/A
ADDR[19:16]/
write int & ext
read external
Single-Chip
ADDR[15:0]/
IQSTAT[3:0]
DATA[15:0]
DATA[15:0]
Emulation
IVD[15:0]
2 cycles
CC[2:0]
ADDR0
LSTRB
1 cycle
1 cycle
1 cycle
EWAIT
R/W
—
Expanded Modes
ADDR[22:20]/A
ADDR[19:16]/
write int & ext
Max. of 2 to 9
read external
or n cycles of
programmed
ADDR[15:0]/
IQSTAT[3:0]
Emulation
DATA[15:0]
DATA[15:0]
Expanded
IVD[15:0]
ext. wait
2 cycles
CC[2:0]
ADDR0
LSTRB
1 cycle
1 cycle
EWAIT
EWAIT
cycles
R/W
Freescale Semiconductor
3
Table
write internal
read internal
ADDR[22:0]
DATA[15:0]
Table 21-3
21-7.
2 cycles
Special
Refer to
ADDR0
LSTRB
1 cycle
1 cycle
1 cycle
Test
R/W
—