CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 602

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 16 Interrupt (S12XINTV1)
16.3.1.2
Read: Anytime
Write: Anytime
602
Address: 0x0126
XILVL[2:0]
Reset
Field
2–0
W
R
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the DMA interrupts
coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
0
0
7
Figure 16-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Priority
high
low
= Unimplemented or Reserved
0
0
6
XILVL2
0
0
0
0
1
1
1
1
Table 16-3. INT_XGPRIO Field Descriptions
Table 16-4. XGATE Interrupt Priority Levels
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
XILVL1
5
0
0
1
1
0
0
1
1
XILVL0
0
0
4
0
1
0
1
0
1
0
1
Description
Interrupt request is disabled
0
0
3
Priority level 1
Priority level 2
Priority level 3
Priority level 4
Priority level 5
Priority level 6
Priority level 7
Meaning
0
2
XILVL[2:0]
Freescale Semiconductor
0
1
1
0