CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 830

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include

mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI,

TAGLO), Read/Write (R/W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ.

When not used for any of these speciﬁc functions, Port E pins 7–2 can be used as general purpose I/O and

pins 1–0 can be used as general purpose inputs.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port

Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.

Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.

Port E Data Register (PORTE)

= Unimplemented or Reserved

Figure 22-11. Port E Data Register (PORTE)

Table 22-12. PORTE Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor