CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 745

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

During BDM hardware accesses and whilst the BDM module is active, S12XCPU monitoring is disabled.

Thus breakpoints, comparators, and bus tracing mapped to the S12XCPU are disabled but XGATE bus

monitoring accessing the S12XDBG registers, including comparator registers, is still possible. While in

active BDM or during hardware BDM accesses, XGATE activity can still be compared, traced and can be

used to generate a breakpoint to the XGATE module. When the S12XCPU enters active BDM Mode

through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed.

The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be

generated if the MCU is secure.

The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the

mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation

Freescale Semiconductor

EXTERNAL TAGHI / TAGLO

XGATE S/W BREAKPOINT REQUEST

READ TRACE DATA (DBG READ DATA BUS)

External Signal Description

Block Diagram

Table 20-1. Mode Dependent Restriction Summary

COMPARATOR A

COMPARATOR B

COMPARATOR C

COMPARATOR D

Figure 20-1. Debug Module Block Diagram

Matches Enabled

MC9S12XDP512 Data Sheet, Rev. 2.21

Active BDM not possible when not enabled

Chapter 20 S12X Debug (S12XDBGV3) Module

BREAKPOINT REQUESTS

S12XCPU & XGATE

STATE SEQUENCER

TRACE BUFFER