CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 483

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Read: Anytime, if AMAP = 0.

Write: Anytime, if AMAP = 0.

Freescale Semiconductor

Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI

and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must

be enabled to use the loop function.

0 Normal operation enabled

1 Loop operation enabled

The receiver input is determined by the RSRC bit.

SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.

0 SCI enabled in wait mode

1 SCI disabled in wait mode

Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register

0 Receiver input internally connected to transmitter output

1 Receiver input connected externally to transmitter

Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.

0 One start bit, eight data bits, one stop bit

1 One start bit, nine data bits, one stop bit

Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the

most signiﬁcant bit position of a received data character or an idle condition on the RXD pin.

0 Idle line wakeup

1 Address mark wakeup

SCI Control Register 1 (SCICR1)

This register is only visible in the memory map if AMAP = 0 (reset

Figure 11-5. SCI Control Register 1 (SCICR1)

Table 11-2. IRSCI Transmit Pulse Width

Table 11-3. SCICR1 Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Narrow Pulse Width

Chapter 11 Serial Communication Interface (S12SCIV5)