CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 788

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 21 External Bus Interface (S12XEBIV2)
21.3
This section provides a detailed description of all registers accessible in the XEBI.
21.3.1
The registers associated with the XEBI block are shown in
21.3.2
The following sub-sections provide a detailed description of each register and the individual register bits.
All control bits can be written anytime, but this may have no effect on the related function in certain
operating modes. This allows specific configurations to be set up before changing into the target operating
mode.
790
EBICTL0
EBICTL1
Register
Name
Memory Map and Register Definition
Module Memory Map
Register Descriptions
W
W
R
R
Depending on the operating mode an available function may be enabled,
disabled or depend on the control register bit. Reading the register bits will
reflect the status of related function only if the current operating mode
allows user control. Please refer the individual bit descriptions.
EWAITE
ITHRS
Bit 7
= Unimplemented or Reserved
6
0
0
Figure 21-2. XEBI Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
HDBE
5
0
NOTE
ASIZ4
4
0
Figure
ASIZ3
3
0
21-2.
EXSTR2
ASIZ2
2
Freescale Semiconductor
EXSTR1
ASIZ1
1
EXSTR0
ASIZ0
Bit 0

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