CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 340

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.22
Read: Anytime
Write: Anytime
All bits reset to zero.
340
DLY[7:0]
Reset
Field
7:0
W
R
DLY7
Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to
calculate the
When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay.
the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts
the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level
of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to
narrow input pulses.
Delay between two active edges of the input signal period should be longer than the selected counter delay.
Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register
DLY7
Delay Counter Control Register (DLYCT)
0
7
0
0
0
0
0
0
0
0
0
0
0
0
1
TSCR1.
DLY6
0
0
0
0
0
0
0
0
0
0
0
1
1
Table 7-28. Delay Counter Select Examples when PRNT = 1
delay.Table 7-27
DLY6
DLY1
0
6
Figure 7-44. Delay Counter Control Register (DLYCT)
0
0
1
1
DLY5
Table 7-27. Delay Counter Select when PRNT = 0
0
0
0
0
0
0
0
0
0
0
1
1
1
Table 7-26. DLYCT Field Descriptions
DLY4
MC9S12XDP512 Data Sheet, Rev. 2.21
DLY5
DLY0
0
0
0
0
0
0
0
0
0
1
1
1
1
shows the delay settings in this case.
0
5
0
1
0
1
DLY3
0
0
0
0
0
0
0
0
1
1
1
1
1
DLY4
0
4
DLY2
0
0
0
0
1
1
1
1
1
1
1
1
1
Description
1024 bus clock cycles
256 bus clock cycles
512 bus clock cycles
DLY1
0
0
1
1
0
0
1
1
1
1
1
1
1
Disabled
DLY3
Delay
0
3
DLY0
0
1
0
1
0
1
0
1
1
1
1
1
1
DLY2
1024 bus clock cycles
128 bus clock cycles
256 bus clock cycles
512 bus clock cycles
Disabled (bypassed)
0
2
12 bus clock cycles
16 bus clock cycles
20 bus clock cycles
24 bus clock cycles
28 bus clock cycles
32 bus clock cycles
64 bus clock cycles
8 bus clock cycles
Delay
Freescale Semiconductor
DLY1
0
1
Table 7-28
DLY0
0
0
shows