CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 110

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
110
CME
0
1
1
1
SCME
X
0
1
1
SCMIE
X
X
0
1
Table 2-13. Outcome of Clock Loss in Pseudo Stop Mode
Clock failure -->
Clock failure -->
Clock Monitor failure -->
Clock failure -->
Scenario 1: OSCCLK recovers prior to exiting pseudo stop mode.
Scenario 2: OSCCLK does not recover prior to exiting pseudo stop mode.
No action, clock loss not detected.
CRG performs Clock Monitor Reset immediately
Some time later OSCCLK recovers.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
or an External Reset is applied.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
or an External RESET is applied.
SCMIF generates self clock mode wakeup interrupt.
– MCU remains in pseudo stop mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag.
– CM no longer indicates a failure,
– 4096 OSCCLK cycles later clock quality check indicates clock o.k.,
– SCM deactivated,
– PLL disabled,
– VREG disabled.
– MCU remains in pseudo stop mode.
– Exit pseudo stop mode using OSCCLK as system clock (SYSCLK),
– Continue normal operation.
– Exit pseudo stop mode using OSCCLK as system clock,
– Start reset sequence.
– MCU remains in pseudo stop mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag,
– Keep performing clock quality checks (could continue infinitely) while
– Exit pseudo stop mode in SCM using PLL clock (f
– Continue to perform additional clock quality checks until OSCCLK is o.k. again.
– Exit pseudo stop mode in SCM using PLL clock (f
– Start reset sequence,
– Continue to perform additional clock quality checks until OSCCLK is o.k.again.
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– SCMIF set.
– Exit pseudo stop mode in SCM using PLL clock (f
– Continue to perform a additional clock quality checks until OSCCLK is o.k. again.
MC9S12XDP512 Data Sheet, Rev. 2.21
in pseudo stop mode.
CRG Actions
SCM
SCM
SCM
) as system clock
) as system clock
) as system clock,
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