CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 653

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.1.3
The S12X architecture implements a number of memory mapping schemes including
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
18.1.4
This subsection lists and briefly describes all operating modes supported by the MMC.
18.1.4.1
1. Resources are also called targets.
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Simultaneous accesses to different resources
Resolution of target bus access collision
Access restriction control from masters to some targets (e.g., RAM write access protection for user
specified areas)
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM and XGATE
ROM control bits to enable the on-chip FLASH or ROM selection
Port replacement registers access control
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
a CPU 8 MByte global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
a BDM 8 MByte global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
a (CPU or BDM) 64 KByte local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64 KBytes visible at any instant can be
considered as the local map accessed by the 16-bit (CPU or BDM) address.
The XGATE 64 Kbyte local map.
Run mode
MMC is functional during normal run mode.
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
S12X Memory Mapping
Modes of Operation
Power Saving Modes
MC9S12XDP512 Data Sheet, Rev. 2.21
1
(internal, external, and peripherals) (see )
Chapter 18 Memory Mapping Control (S12XMMCV3)
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