CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 328

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

Read: Anytime

Write used in the ﬂag clearing mechanism. Writing a one to the ﬂag clears the ﬂag. Writing a zero will not

affect the current status of the bit.

All bits reset to zero.

TFLG1 indicates when interrupt conditions have occurred. The ﬂags can be cleared via the normal ﬂag

clearing mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (reference TFFCA

Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a

timer interrupt to be generated after capturing two values in the capture and holding registers, instead of

generating an interrupt for every capture.

Section 7.3.2.6, “Timer System Control Register 1

Input Capture/Output Compare Channel “x” Flag — A CxF ﬂag is set when a corresponding input capture or

output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be

set by 8-bit pulse accumulators PAC3–PAC0.

If the delay counter is enabled, the CxF ﬂag will not be set until after the delay.

Main Timer Interrupt Flag 1 (TFLG1)

When TFFCA = 1, the ﬂags cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference

System Control Register 1

Figure 7-17. Main Timer Interrupt Flag 1 (TFLG1)

Table 7-16. TFLG1 Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Section 7.3.2.6, “Timer

Freescale Semiconductor