CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1077

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
26.3.2.2
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
26.3.2.3
This register is reserved for factory testing and is not accessible.
Freescale Semiconductor
EDIV[5:0]
EDIVLD
PRDIV8
Reset
Reset
Field
5–0
7
6
W
W
R
R
EDIVLD
Clock Divider Loaded
0 Register has not been written.
1 Register has been written to since the last reset.
0 The oscillator clock is directly fed into the ECLKDIV divider.
1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input
oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to
Section 26.4.1.1, “Writing the ECLKDIV Register”
Enable Prescalar by 8
RESERVED1
RESERVED2
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
PRDIV8
Figure 26-4. EEPROM Clock Divider Register (ECLKDIV)
0
0
0
6
6
Table 26-3. ECLKDIV Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
EDIV5
0
0
0
5
5
Figure 26-5. RESERVED1
EDIV4
0
0
0
4
4
Description
for more information.
EDIV3
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2)
0
0
0
3
3
EDIV2
0
0
0
2
2
EDIV1
0
0
0
1
1
EDIV0
0
0
0
0
0
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