CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 329

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
7.3.2.13
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
All bits reset to zero.
TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in
Freescale Semiconductor
Reset
Field
TOF
7
Section 7.3.2.6, “Timer System Control Register 1
W
R
TOF
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000.
Main Timer Interrupt Flag 2 (TFLG2)
0
7
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
= Unimplemented or Reserved
0
0
6
Figure 7-18. Main Timer Interrupt Flag 2 (TFLG2)
Table 7-17. TFLG2 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
(TSCR1)”.
NOTE
0
0
4
Description
(TSCR1)”).
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
3
Section 7.3.2.6, “Timer
0
0
2
0
0
1
0
0
0
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