CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 327

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.11
Read or write: Anytime
All bits reset to zero.
Freescale Semiconductor
PR[2:0]
Reset
TCRE
Field
TOI
2:0
7
3
W
R
Timer Overflow Interrupt Enable
0 Timer overflow interrupt disabled.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output
compare. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset disabled and counter free runs.
1 Counter reset by a successful output compare on channel 7.
Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register
Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT
bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized
edge where all prescale counter stages equal zero. See
TOI
Timer System Control Register 2 (TSCR2)
0
7
TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000.
= Unimplemented or Reserved
Figure 7-16. Timer System Control Register 2 (TSCR2)
0
0
6
PR2
0
0
0
0
1
1
1
1
Table 7-14. TSCR2 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 7-15. Prescaler Selection
0
0
5
PR1
0
0
1
1
0
0
1
1
PR0
0
0
4
0
1
0
1
0
1
0
1
Description
Table
TCRE
Prescale Factor
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
3
7-15.
128
16
32
64
1
2
4
8
PR2
0
2
PR1
0
1
PR0
0
0
327