CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 392

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by
the low order CAEx bit. The high order CAEx bit has no effect.
Table 8-11
mode.
8.4.2.8
Table 8-12
or center aligned) and 8-bit (normal) or 16-bit (concatenation).
8.5
The reset state of each individual bit is listed within the
details the registers and their bit-fields. All special functions or modes which are initialized during or just
following reset are described within this section.
392
The 8-bit up/down counter is configured as an up counter out of reset.
All the channels are disabled and all the counters do not count.
Resets
is used to summarize which channels are used to set the various control bits when in 16-bit
summarizes the boundary conditions for the PWM regardless of the output mode (left aligned
1
PWM Boundary Cases
Counter = $00 and does not count.
(indicates no duty)
(indicates no duty)
CONxx
CON67
CON45
CON23
CON01
>= PWMPERx
>= PWMPERx
PWMDTYx
$00
$00
XX
XX
Table 8-11. 16-bit Concatenation Mode Summary
PWMEx
PWME7
PWME5
PWME3
PWME1
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 8-12. PWM Boundary Cases
(indicates no period)
(indicates no period)
PWMPERx
PPOLx
PPOL7
PPOL5
PPOL3
PPOL1
>$00
>$00
$00
$00
XX
XX
1
1
PCLKx
Section 8.3.2, “Register Descriptions”
PCLK7
PCLK5
PCLK3
PCLK1
PPOLx
1
0
1
0
1
0
CAEx
CAE7
CAE5
CAE3
CAE1
PWMx Output
Always high
Always high
Always high
Always low
Always low
Always low
Output
PWMx
PWM7
PWM5
PWM3
PWM1
Freescale Semiconductor
which

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