CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 661

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.2.3
Read: Anytime
Write: Anytime
The global page index register is used to construct a 23 bit address in the global map format. It is only used
when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX,
GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global
address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see
Figure
Freescale Semiconductor
Address: 0x0010
GP[6:0]
Reset
Field
6–0
W
R
18-7).
Bit22
LDX
MOVB
GLDAA
Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is
to be accessed.
Global Page Index Register (GPAGE)
0
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Example 18-1. This example demonstrates usage of the GPAGE register
GPAGE Register [6:0]
#0x5000
#0x14, GPAGE
X
= Unimplemented or Reserved
GP6
0
6
Figure 18-6. Global Page Index Register (GPAGE)
Figure 18-7. GPAGE Address Mapping
Table 18-8. GPAGE Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
GP5
0
5
;Set GPAGE offset to the value of 0x5000
;Initialize GPAGE register with the value of 0x14
;Load Accu A from the global address 0x14_5000
Global Address [22:0]
Bit16
CAUTION
Bit15
GP4
0
4
Description
GP3
0
3
CPU Address [15:0]
Chapter 18 Memory Mapping Control (S12XMMCV3)
GP2
0
2
GP1
0
1
Bit 0
GP0
0
0
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