R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 95

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
(4)
Register indirect with post-decrement—@ERn−
The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field of the instruction code. After the
memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the
remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word
access, or 4 for longword access.
If the contents of a general register which is also used as an address register is written to memory
using this addressing mode, data to be written is the contents of the general register after
calculating an effective address. If the same general register is specified in an instruction and two
effective addresses are calculated, the contents of the general register after the first calculation of
an effective address is used in the second calculation of an effective address.
Example 1:
MOV.W R0, @ER0+
When ER0 before execution is H'12345678, H'567A is written at H'12345678.
Example 2:
MOV.B @ER0+, @ER0+
When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at
H'00001001.
After execution, ER0 is H'00001002.
Rev. 3.00 Mar. 14, 2006 Page 57 of 804
REJ09B0104-0300