R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 197
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
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Figure 7.2 shows an example of the signal timing in dual address mode and figure 7.3 shows the
operation in dual address mode.
Address B
Address T
A
A
Figure 7.2 Example of Signal Timing in Dual Address Mode
B
Address bus
RD
WR
TEND
Figure 7.3 Operations in Dual Address Mode
DMA read cycle DMA write cycle
DSAR
Transfer
Address update setting is as follows:
Source address increment
Fixed destination address
DDAR
Rev. 3.00 Mar. 14, 2006 Page 159 of 804
Section 7 DMA Controller (DMAC)
REJ09B0104-0300
Address T
B
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