R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 312
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
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Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.15 TIORH_0
[Legend]
X: Don't care
Note: When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and Pφ/1 is used as the TCNT_1
Rev. 3.00 Mar. 14, 2006 Page 274 of 804
REJ09B0104-0300
Bit 7
IOB3
0
0
0
0
0
0
0
0
1
1
1
1
count clock, this setting is invalid and input capture is not generated.
Bit 6
IOB2
0
0
0
0
1
1
1
1
0
0
0
1
Bit 5
IOB1
0
0
1
1
0
0
1
1
0
0
1
x
Bit 4
IOB0
0
1
0
1
0
1
0
1
0
1
x
x
TGRB_0
Function
Output
compare
register
Input
capture
register
TIOCB0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCB0 pin
Input capture at rising edge
Capture input source is TIOCB0 pin
Input capture at falling edge
Capture input source is TIOCB0 pin
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*
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