R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 432

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 12 Serial Communication Interface (SCI)
Rev. 3.00 Mar. 14, 2006 Page 394 of 804
REJ09B0104-0300
Bit
5
4
Bit Name
ORER
ERS
Initial
Value
0
0
R/W
R/(W)* Overrun Error
R/(W)* Error Signal Status
Description
Indicates that an overrun error has occurred during
reception and the reception ends abnormally.
[Setting condition]
[Clearing condition]
[Setting condition]
[Clearing condition]
When the next serial reception is completed while
RDRF = 1
In RDR, the receive data prior to an overrun error
occurrence is retained, but data received following the
overrun error occurrence is lost. When the ORER flag
is set to 1, subsequent serial reception cannot be
performed. Note that, in clocked synchronous mode,
serial transmission also cannot continue.
When 0 is written to ORER after reading ORER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the ORER
flag is not affected and retains its previous value.
When a low error signal is sampled
When 0 is written to ERS after reading ERS = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)

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