R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 422

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Serial Communication Interface (SCI)
Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
Rev. 3.00 Mar. 14, 2006 Page 384 of 804
REJ09B0104-0300
Bit
7
6
5
4
3
2
Bit Name
GM
BLK
PE
O/E
BCP1
BCP0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
GSM Mode
Setting this bit to 1 allows GSM mode operation. In GSM
mode, the TEND set timing is put forward to 11.0 etu from
the start and the clock output control function is
appended. For details, see sections 12.7.6, Data
Transmission (Except in Block Transfer Mode) and
12.7.8, Clock Output Control.
Setting this bit to 1 allows block transfer mode operation.
For details, see section 12.7.3, Block Transfer Mode.
Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. Set this bit to 1 in smart card interface mode.
Parity Mode (valid only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card interface
mode, see section 12.7.2, Data Format (Except in Block
Transfer Mode).
Basic Clock Pulse 1,0
These bits select the number of basic clock cycles in a 1-
bit data transfer time in smart card interface mode.
00: 32 clock cycles (S = 32)
01: 64 clock cycles (S = 64)
10: 372 clock cycles (S = 372)
11: 256 clock cycles (S = 256)
For details, see section 12.7.4, Receive Data Sampling
Timing and Reception Margin. S is described in section
12.3.9, Bit Rate Register (BRR).