R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 128

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
5.3.2
CPUPCR sets whether or not the CPU has priority over the DMAC. The interrupt exception
handling by the CPU can be given priority over that of the DMAC transfer. The priority level of
the DMAC for each channel is set by the DMAC control register.
Bit
Bit Name
Initial Value
R/W
Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.
Rev. 3.00 Mar. 14, 2006 Page 90 of 804
REJ09B0104-0300
Bit
3
2 to 0
Bit
7
6 to 4
Bit Name
NMIEG

Bit Name
CPUPCE

CPU Priority Control Register (CPUPCR)
CPUPCE
R/W
7
0
Initial
Value
0
All 0
Initial
Value
0
All 0
R/W
—
6
0
R/W
R/W
R/W
R/W
R/W
R
R/W
—
5
0
Description
CPU Priority Control Enable
Controls the CPU priority control function. Setting this bit
to 1 enables the CPU priority control over the DMAC.
0: CPU always has the lowest priority
1: CPU priority control enabled
Reserved
This bit is always read as 0. The write value should
always be 0.
Description
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of NMI
1: Interrupt request generated at rising edge of NMI
Reserved
These are read-only bits and cannot be modified.
R/W
—
4
0
input
input
IPSETE
R/W
3
0
CPUP2
R/(W)*
2
0
CPUP1
R/(W)*
1
0
CPUP0
R/(W)*
0
0