R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 557

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.3.5
SSSR is a status flag register for interrupts.
Bit
7
6
5, 4
Bit
Bit Name
Initial Value
R/W
Bit Name

ORER

SS Status Register (SSSR)
R/W
—
7
0
Initial
Value
0
0
All 0
ORER
R/W
6
0
R/W

R/W
R/W
R/W
—
5
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either.
[Setting condition]
When one byte of the next reception is completed with
RDRF = 1
[Clearing condition]
When writing 0 after reading ORER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Reserved
These bits are always read as 0. The write value should
always be 0.
Section 14 Synchronous Serial Communication Unit (SSU)
R/W
—
4
0
TEND
R/W
3
0
Rev. 3.00 Mar. 14, 2006 Page 519 of 804
TDRE
R/W
2
1
RDRF
R/W
1
0
REJ09B0104-0300
R/W
CE
0
0