R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 378

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.7
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the write data.
Figure 9.50 shows the timing in this case.
9.9.8
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 9.51 shows the timing in this case.
Rev. 3.00 Mar. 14, 2006 Page 340 of 804
REJ09B0104-0300
Conflict between Buffer Register Write and Compare Match
Conflict between TGR Read and Input Capture
Figure 9.50 Conflict between Buffer Register Write and Compare Match
P
Address
Read
Input capture
signal
TGR
Internal data
bus
P
Address
Write
Compare match
signal
Buffer register
TGR
Figure 9.51 Conflict between TGR Read and Input Capture
X
TGR read cycle
TGR write cycle
Buffer register
N
T1
T1
address
address
TGR
M
T2
T2
M
M
M
Data written to buffer register