R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 643

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(2)
The procedures for download of the on-chip program, initialization, and programming are shown
in figure 17.11.
The procedure program must be executed in an area other than the flash memory to be
programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-
chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM
and user MAT) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data.
The following description assumes that the area to be programmed on the user MAT is erased and
that program data is prepared in the consecutive area.
Programming Procedure in User Program Mode
Set SCO to 1 after initializing
VBR and execute download
JSR FTDAR setting
Select on-chip program
to be downloaded and
destination by FTDAR
procedure program
Start programming
specify download
Set FKEY to H'A5
Set the FPEFEQ
Clear FKEY to 0
DPFR
Initialization
FPFR
parameter
Figure 17.11 Programming Procedure in User Program Mode
1
Yes
Yes
0?
0?
Initialization error processing
32
Download error processing
No
No
1.
2.
3.
4.
5.
6.
7.
8.
Section 17 Flash Memory (0.18-(m F-ZTAT Version)
No
Rev. 3.00 Mar. 14, 2006 Page 605 of 804
Disable interrupts and bus
JSR FTDAR setting
Set parameters to ER1
(FMPAR and FMPDR)
procedure program
End programming
Set FKEY to H'5A
master operation
Clear FKEY to 0
programming is
other than CPU
Required data
Programming
FPFR
completed?
and ER0
1
Yes
Yes
0?
16
REJ09B0104-0300
Clear FKEY and
No
error processing
programming
9.
10.
11.
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14.
15.