R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 581

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(4)
Figure 14.17 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bits to 1.
[1]
[3]
[4]
Data Transmission/Reception
No
Read received data in SSRDR
Read receive data in SSRDR
RDRF automatically cleared
Overrun error processing
Consecutive data reception?
Clear ORER in SSSR
End reception
End reception
Initial setting
Read SSSR
ORER = 1?
RDRF = 1?
RE = 0
Start
Figure 14.16 Flowchart Example of Data Reception
Yes
Yes
No
(Clock Synchronous Communication Mode)
Yes
No
[2]
[1]
[2], [4] Receive error processing:
[3]
Section 14 Synchronous Serial Communication Unit (SSU)
Note: Hatching boxes represent SSU internal operations.
Initial setting:
Specify the receive data format.
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
Rev. 3.00 Mar. 14, 2006 Page 543 of 804
REJ09B0104-0300