R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 505
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
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Bit
11
10
9
Bit Name
IRR3
IRR2
IRR1
Initial
Value
0
0
0
R/W
R/(W)*
R
R
Description
Transmit Overload Warning Interrupt Flag
Status flag indicating the error warning state
caused by the transmit error counter.
[Setting condition]
•
[Clearing condition]
•
(When the CPU is used to clear this flag by
writing 1 while the corresponding interrupt is
enabled, be sure to read the flag after writing 1 to
it.)
Remote Frame Request Interrupt Flag When
MBIMR = 0
Status flag indicating that a remote frame has
been received in a mailbox (buffer).
[Setting condition]
•
[Clearing condition]
•
Receive Message Interrupt Flag When
MBIMR = 0
Status flag indicating that a mailbox (buffer)
receive message has been received normally.
[Setting condition]
•
[Clearing condition]
•
When TEC ≥ 96
Writing 1
When remote frame reception is completed,
when corresponding MBIMR = 0
Clearing of all bits in RFPR (remote request
register)
When data frame or remote frame reception is
completed, when corresponding MBIMR = 0
Clearing of all bits in RXPR (receive complete
register)
Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 467 of 804
REJ09B0104-0300
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