R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 328

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.4
TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER
registers, one for each channel.
Rev. 3.00 Mar. 14, 2006 Page 290 of 804
REJ09B0104-0300
Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
Note: * Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should always be 0.
Bit Name
TTGE*

TCIEU
TCIEV
Timer Interrupt Enable Register (TIER)
TTGE*
R/W
7
0
Initial
value
0
1
0
0
—
R
6
1
R/W
R/W
R
R/W
R/W
TCIEU
R/W
5
0
A/D Conversion Start Request Enable
Enables/disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
Reserved
This is a read-only bit and cannot be modified.
Underflow Interrupt Enable
Enables/disables interrupt requests (TCIU) by the TCFU
flag when the TCFU flag in TSR is set to 1 in channels 1,
2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is a read-only bit
and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Overflow Interrupt Enable
Enables/disables interrupt requests (TCIV) by the TCFV
flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
Description
TCIEV
R/W
4
0
TGIED
R/W
3
0
TGIEC
R/W
2
0
TGIEB
R/W
1
0
TGIEA
R/W
0
0