R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 696

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 17 Flash Memory (0.18-(m F-ZTAT Version)
17.14
1. The initial state of the product at its shipment is in the erased state. For the product whose
2. For the PROM programmer suitable for programmer mode in this LSI and its program version,
3. If the socket, socket adapter, or product index does not match the specifications, too much
4. Use a PROM programmer that supports the device with 256-kbyte on-chip flash memory and
5. Do not remove the chip from the PROM programmer nor input a reset signal during
6. The flash memory is not accessible until FKEY is cleared after programming/erasing starts. If
7. At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory
8. In on-board programming mode or programmer mode, programming of the 128-byte
9. When the chip is to be reprogrammed with the programmer after execution of programming or
10. To program the flash memory, the program data and program must be allocated to addresses
11. The programming program that includes the initialization routine and the erasing program that
Rev. 3.00 Mar. 14, 2006 Page 658 of 804
REJ09B0104-0300
revision of erasing is undefined, we recommend to execute automatic erasure for checking the
initial state (erased state) and compensating.
refer to the instruction manual of the socket adapter.
current flows and the product may be damaged.
5.0-V programming voltage. Do not select HN28F101 and 3.3-V programming voltage with
the programmer parameters. Use only the specified socket adapter.
programming/erasing in which a high voltage is applied to the flash memory. Doing so may
damage the flash memory permanently. If a reset is input accidentally, the reset must be
released after the reset input period of at least 100 µs.
the operating mode is changed and this LSI is restarted by a reset immediately after
programming/erasing has finished, secure the reset input period (period of RES = 0) of at least
100 µs. Transition to the reset state during programming/erasing is inhibited. If a reset is input
accidentally, the reset must be released after the reset input period of at least 100 µs.
to hardware protection state. This power on/off timing must also be satisfied at a power-off and
power-on caused by a power failure and other factors.
programming-unit block must be performed only once. Perform programming in the state
where the programming-unit block is fully erased.
erasure in on-board programming mode, it is recommended that automatic programming is
performed after execution of automatic erasure.
which are higher than those of the external interrupt vector table and H'FF must be written to
all the system reserved areas in the exception handling vector table.
includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock
frequency is 40 MHz, it takes 42 µs at the maximum to download each program.
Usage Notes

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