R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 533

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(1)
CPU interrupt source settings are made in the interrupt mask register (IMR) and mailbox interrupt
register (MBIMR). The message to be received is also specified. Data frame and remote frame
receive wait interrupt requests can be generated for individual mailboxes in the MBIMR.
(2)
To receive a message, the message identifier must be set in advance in the message control
registers (MCx[1] to MCx[8]) for the receiving mailbox. When a message is received, all the bits
in the receive message identifier are compared with those in each message control register
identifier, and if a complete match is found, the message is stored in the matching mailbox.
Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don't Care settings. The LAFM
setting can be made only for mailbox 0. By setting the Don't Care for all the bits in the receive
message identifier, messages of multiple identifiers can be received.
Examples:
• When the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of
• When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is
message identifier can be received by mailbox 1:
Identifier 1:
000_0000_0011 (0: Care, 1: Don't Care), a total of four kinds of message identifiers can be
received by mailbox 0:
Identifier 1:
Identifier 2:
Identifier 3:
Identifier 4:
CPU interrupt source settings
Arbitration field setting
010_1010_1010
010_1010_1000
010_1010_1001
010_1010_1010
010_1010_1011
Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 495 of 804
REJ09B0104-0300