R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 17

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.9 Usage Notes ....................................................................................................................... 442
Section 13 Controller Area Network (HCAN) ..................................................449
13.1 Features.............................................................................................................................. 449
13.2 Input/Output Pins ............................................................................................................... 451
13.3 Register Descriptions ......................................................................................................... 452
13.4 Operation ........................................................................................................................... 484
12.9.1 Module Stop Mode Setting ................................................................................... 442
12.9.2 Break Detection and Processing ........................................................................... 442
12.9.3 Mark State and Break Detection ........................................................................... 442
12.9.4 Receive Error Flags and Transmit Operations
12.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 443
12.9.6 Restrictions on Using DMAC............................................................................... 443
12.9.7 SCI Operations during Mode Transitions ............................................................. 444
13.3.1 Master Control Register (MCR) ........................................................................... 453
13.3.2 General Status Register (GSR) ............................................................................. 454
13.3.3 Bit Configuration Register (BCR) ........................................................................ 456
13.3.4 Mailbox Configuration Register (MBCR) ............................................................ 458
13.3.5 Transmit Wait Register (TXPR) ........................................................................... 459
13.3.6 Transmit Wait Cancel Register (TXCR)............................................................... 460
13.3.7 Transmit Acknowledge Register (TXACK) ......................................................... 461
13.3.8 Abort Acknowledge Register (ABACK) .............................................................. 462
13.3.9 Receive Complete Register (RXPR)..................................................................... 463
13.3.10 Remote Request Register (RFPR)......................................................................... 464
13.3.11 Interrupt Register (IRR)........................................................................................ 465
13.3.12 Mailbox Interrupt Mask Register (MBIMR)......................................................... 470
13.3.13 Interrupt Mask Register (IMR) ............................................................................. 471
13.3.14 Receive Error Counter (REC)............................................................................... 473
13.3.15 Transmit Error Counter (TEC).............................................................................. 473
13.3.16 Unread Message Status Register (UMSR)............................................................ 474
13.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)............................................ 475
13.3.18 Message Control (MC0 to MC15) ........................................................................ 478
13.3.19 Message Data (MD0 to MD15) ............................................................................ 481
13.3.20 HCAN Monitor Register (HCANMON)............................................................... 483
13.4.1 Hardware and Software Resets ............................................................................. 484
13.4.2 Initialization after Hardware Reset ....................................................................... 484
13.4.3 Message Transmission .......................................................................................... 490
13.4.4 Message Reception ............................................................................................... 494
13.4.5 HCAN Sleep Mode............................................................................................... 498
(Clocked Synchronous Mode Only) ..................................................................... 442
Rev. 3.00 Mar. 14, 2006 Page xvii of xxxviii