R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 163

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

This LSI has an on-chip bus controller (BSC) that has a bus arbitration function and controls the
operation of the internal bus masters; CPU and DMAC.
6.1
• Write data buffer function
• Bus arbitration function
• Multi-clock function
A block diagram of the bus controller is shown in figure 6.1.
Write access to an on-chip peripheral module and access to the on-chip memory can be
performed in parallel.
Includes a bus arbiter that arbitrates bus mastership between the CPU and DMAC.
Bus mastership can be shared between the CPU and DMAC when a conflict occurs.
On-chip peripheral functions can be synchronized with the on-chip peripheral module clock
(Pφ).
Features
DMAC bus mastership acknowledge signal
CPU bus mastership acknowledge signal
[Legend]
BCR2:
Section 6 Bus Controller (BSC)
DMAC bus mastership request signal
CPU bus mastership request signal
Figure 6.1 Block Diagram of Bus Controller
Bus control register 2
Internal data bus
Internal bus
control signals
Control register
Internal
bus
arbiter
Internal bus
control unit
Rev. 3.00 Mar. 14, 2006 Page 125 of 804
BCR2
Section 6 Bus Controller (BSC)
REJ09B0104-0300