R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 580

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Synchronous Serial Communication Unit (SSU)
(3)
Figure 14.15 shows an example of reception operation, and figure 14.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
Rev. 3.00 Mar. 14, 2006 Page 542 of 804
REJ09B0104-0300
SSCK
SSO
RDRF
LSI operation
User operation
Data Reception
Dummy-read SSRDR
Bit 0
Figure 14.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
1 frame
Bit 7
RXI interrupt
generated
Bit 0
Read data from SSRDR
1 frame
RXI interrupt
generated
Bit 7
Bit 0
Read data from SSRDR
RXI interrupt
Bit 7
generated