R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 196

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
When the auto request setting is selected as the activation source, the cycle stealing or burst access
can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer
counter is stopped and the transfer is continued without the limitation of the transfer count.
7.4
7.4.1
(1)
In dual address mode, the transfer source address is specified in DSAR and the transfer destination
address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data
bus width is less than the data access size or the access address is not aligned with the boundary of
the data access size, the number of bus cycles are needed more than two because one bus cycle is
divided into multiple bus cycles).
In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data
is written to the transfer destination address.
The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters,
refresh cycle, and external bus release cycle) are not generated between read and write cycles.
The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is
output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is
also output in the idle cycle. The DACK signal is not output.
Rev. 3.00 Mar. 14, 2006 Page 158 of 804
REJ09B0104-0300
Dual Address Mode
Operations
Address Modes