R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 466

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Serial Communication Interface (SCI)
Rev. 3.00 Mar. 14, 2006 Page 428 of 804
REJ09B0104-0300
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
Note: When switching from transmit or receive operation to
simultaneous transmit and receive operations, first clear the
TE bit and RE bit to 0, then set both these bits to 1
simultaneously.
No
No
No
Clear TE and RE bits in SCR to 0
Write transmit data to TDR and
Read receive data in RDR, and
clear TDRE flag in SSR to 0
clear RDRF flag in SSR to 0
Start transmission/reception
Read ORER flag in SSR
Read RDRF flag in SSR
Read TDRE flag in SSR
All data received?
Initialization
ORER = 1
TDRE = 1
RDRF = 1
<End>
Yes
Yes
Yes
No
Error processing
Yes
[1]
[2]
[4]
[5]
[3]
[1] SCI initialization:
[2] SCI state check and transmit data
[3] Receive error processing:
[4] SCI state check and receive data
[5] Serial transmission/reception
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0. Transition of the
TDRE flag from 0 to 1 can also be
identified by a TXI interrupt.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to
0. Reception cannot be resumed if
the ORER flag is set to 1.
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
However, the TDRE flag is checked
and cleared automatically when the
DMAC is initiated by a transmit data
empty interrupt (TXI) request and
writes data to TDR. Similarly, the
RDRF flag is cleared automatically
when the DMAC is initiated by a
receive data full interrupt (RXI) and
reads data from RDR.