R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 26

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 9.26 Example of Phase Counting Mode 1 Operation ...................................................... 320
Figure 9.27 Example of Phase Counting Mode 2 Operation ...................................................... 321
Figure 9.28 Example of Phase Counting Mode 3 Operation ...................................................... 322
Figure 9.29 Example of Phase Counting Mode 4 Operation ...................................................... 323
Figure 9.30 Phase Counting Mode Application Example........................................................... 325
Figure 9.31 Count Timing in Internal Clock Operation.............................................................. 330
Figure 9.32 Count Timing in External Clock Operation ............................................................ 330
Figure 9.33 Output Compare Output Timing ............................................................................. 331
Figure 9.34 Input Capture Input Signal Timing.......................................................................... 331
Figure 9.35 Counter Clear Timing (Compare Match) ................................................................ 332
Figure 9.36 Counter Clear Timing (Input Capture) .................................................................... 332
Figure 9.37 Buffer Operation Timing (Compare Match) ........................................................... 333
Figure 9.38 Buffer Operation Timing (Input Capture) ............................................................... 333
Figure 9.39 TGI Interrupt Timing (Compare Match) ................................................................. 334
Figure 9.40 TGI Interrupt Timing (Input Capture) ..................................................................... 334
Figure 9.41 TCIV Interrupt Setting Timing................................................................................ 335
Figure 9.42 TCIU Interrupt Setting Timing................................................................................ 335
Figure 9.43 Timing for Status Flag Clearing by CPU ................................................................ 336
Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (1)..................................... 336
Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2)..................................... 337
Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 337
Figure 9.47 Conflict between TCNT Write and Clear Operations ............................................. 338
Figure 9.48 Conflict between TCNT Write and Increment Operations...................................... 339
Figure 9.49 Conflict between TGR Write and Compare Match ................................................. 339
Figure 9.50 Conflict between Buffer Register Write and Compare Match ................................ 340
Figure 9.51 Conflict between TGR Read and Input Capture...................................................... 340
Figure 9.52 Conflict between TGR Write and Input Capture..................................................... 341
Figure 9.53 Conflict between Buffer Register Write and Input Capture .................................... 341
Figure 9.54 Conflict between Overflow and Counter Clearing .................................................. 342
Figure 9.55 Conflict between TCNT Write and Overflow ......................................................... 342
Section 10 Programmable Pulse Generator (PPG)
Figure 10.1 Block Diagram of PPG............................................................................................ 345
Figure 10.2 Schematic Diagram of PPG..................................................................................... 356
Figure 10.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 356
Figure 10.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 357
Figure 10.5 Normal Pulse Output Example (5-Phase Pulse Output) .......................................... 358
Figure 10.6 Non-Overlapping Pulse Output ............................................................................... 359
Figure 10.7 Non-Overlapping Operation and NDR Write Timing ............................................. 360
Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 361
Figure 10.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) ..................... 362
Figure 10.10 Inverted Pulse Output (Example) .......................................................................... 364
Figure 10.11 Pulse Output Triggered by Input Capture (Example)............................................ 365
Rev. 3.00 Mar. 14, 2006 Page xxvi of xxxviii