R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 64

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
• Stack Structure
Rev. 3.00 Mar. 14, 2006 Page 26 of 804
REJ09B0104-0300
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch
address.
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The
EXR contents are saved or restored regardless of whether or not EXR is in use.
SP
H'00000000
H'00000001
H'00000002
H'00000003
H'00000004
H'00000005
H'00000006
H'00000007
Figure 2.6 Exception Vector Table (Maximum Modes)
(a) Subroutine Branch
Figure 2.7 Stack Structure (Maximum Mode)
(32 bits)
PC
Reset exception vector
SP
(b) Exception Handling
Exception vector table
(32 bits)
CCR
EXR
PC