R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 216

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in
longwords. If the upper word and lower word are read separately, incorrect data may be read from
since the contents of DTCR during the transfer may be updated regardless of the access by the
CPU. Moreover, DTCR for the channel being transferred must not be written to.
When a conflict occurs between the address update by DMA transfer and write access by the CPU,
the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and
write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the
transfer is stopped.
(4)
DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and
bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat
size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size
and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to
change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the
BKSZ bits.
Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words.
DBSR for the channel being transferred must not be written to.
(5)
Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is
automatically cleared to 0 according to the DMA transfer state by the DMAC.
The conditions for clearing the DTE bit by the DMAC are as follows:
• When the total size of transfers is completed
• When a transfer is completed by a transfer size error interrupt
• When a transfer is completed by a repeat size end interrupt
• When a transfer is completed by an extended repeat area overflow interrupt
• When a transfer is stopped by an NMI interrupt
• When a transfer is stopped by and address error
• Reset state
• Hardware standby mode
• When a transfer is stopped by writing 0 to the DTE bit
Rev. 3.00 Mar. 14, 2006 Page 178 of 804
REJ09B0104-0300
DMA Block Size Register (DBSR)
DTE Bit in DMDR