R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 596

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 A/D Converter
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
Rev. 3.00 Mar. 14, 2006 Page 558 of 804
REJ09B0104-0300
Notes: 1.
ADST
ADF
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Channel 2 (AN2)
operation state
Channel 3 (AN3)
operation state
ADDRA
ADDRB
ADDRC
ADDRD
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
2.
Data being converted is ignored.
indicates the timing of instruction execution by software.
Waiting for
conversion
Waiting for conversion
Waiting for conversion
Waiting for conversion
(Scan Mode, Three Channels (AN0 to AN2) Selected)
Figure 15.4 Example of A/D Conversion
Set *
A/D
conver-
sion 1
1
Transfer
A/D conversion consecutive execution
A/D
conver-
sion 2
Waiting for conversion
A/D conversion result 1
A/D
conver-
sion 3
Waiting for conversion
A/D conversion time
A/D
conver-
sion 4
A/D conversion result 2
A/D conversion result 3
A/D
conver-
sion 5
A/D conversion result 4
Waiting for conversion
Waiting for conversion
*
Clear *
2
Waiting for
conversion
1
Clear *
1