R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 125

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.1
• Two interrupt control modes
• Priority can be assigned by the interrupt priority register (IPR)
• Independent vector addresses
• 16 external interrupts
• DMAC control
• CPU priority control function
Note: * A DMA address error is generated within the DMAC.
Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the
interrupt control register (INTCR).
IPR provides for setting interrupt priory. Eight levels can be set for each module for all
interrupts except for the interrupt requests listed below. The following six interrupt requests
are given priority of 8, therefore they are accepted at all times.
 NMI
 General illegal instructions
 Trace
 Trap instructions
 CPU address error
 DMA address error*
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ14 to IRQ0.
DMAC can be activated by means of interrupts.
The priority levels can be assigned to the CPU and DMAC. The priority level of the CPU can
be automatically assigned on an exception generation. Priority can be given to the CPU
interrupt exception handling over that of the DMAC transfer.
Features
Section 5 Interrupt Controller
Rev. 3.00 Mar. 14, 2006 Page 87 of 804
Section 5 Interrupt Controller
REJ09B0104-0300