R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 670

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 Flash Memory (0.18-(m F-ZTAT Version)
(1)
The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the
host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate
has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment
sequence is shown in figure 17.22.
(2)
After adjustment of the bit rate, the protocol for serial communications between the host and the
boot program is as shown below.
1. One-byte commands and one-byte responses
2. n-byte commands or n-byte responses
3. Error response
4. Programming of 128 bytes
Rev. 3.00 Mar. 14, 2006 Page 632 of 804
REJ09B0104-0300
These one-byte commands and one-byte responses consist of the inquiries and the ACK for
successful completion.
These commands and responses are comprised of n bytes of data. These are selections and
responses to inquiries.
The program data size is not included under this heading because it is determined in another
command.
The error response is a response to inquiries. It consists of an error response and an error code
and comes two bytes.
The size is not specified in commands. The size of n is indicated in response to the
programming unit inquiry.
Bit-Rate-Adjustment State
Communications Protocol
Host
Figure 17.22 Bit-Rate-Adjustment Sequence
H'00 (completion of adjustment)
H'E6 (boot response)
H'00 (30 times maximum)
(H'FF (error))
H'55
Measuring the
Boot program
1-bit length