R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 570

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Mar. 14, 2006 Page 532 of 804
REJ09B0104-0300
User operation
User operation
User operation
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0
(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0
(3) When 32-bit data length is selected (SSTDR0 and SSTDR3 are valid) with CPOS = 0 and CPHS = 0
LSI operation
LSI operation
LSI operation
(MSB first)
(MSB first)
(LSB first)
(LSB first)
SSCK
TDRE
TEND
SSCK
TDRE
TEND
SSCK
TDRE
TEND
SCS
SSO
SCS
SSO
SSO
SCS
SSO
SSO
Figure 14.5 Example of Transmission Operation (SSU Mode)
Data written to SSTDR0 to SSTDR1
Data written to SSTDR0
Data written to SSTDR0 and SSTDR1
TXI interrupt
generated
Bit
Bit
Bit
Bit
Bit
0
0
7
0
7
SSTDR
SSTDR
Bit
Bit
Bit
(LSB first transmission)
to
to
1
1
6
Bit
Bit
Bit
Bit
Bit
5
2
2
7
0
1 frame
SSTDR1
SSTDR0
SSTDR0
Bit
Bit
Bit
Bit
Bit
3
3
4
0
7
SSTDR
SSTDR
Bit
Bit
Bit
to
to
4
4
3
TXI interrupt generated TEI interrupt generated
1 frame
Bit
Bit
Bit
Bit
Bit
TEI interrupt
5
5
2
7
0
generated
Bit
Bit
Bit
Bit
Bit
6
6
1
0
7
SSTDR
1 frame
SSTDR
TXI interrupt generated
Bit
Bit
Bit
to
to
7
7
0
Bit
Bit
Bit
Bit
0
7
0
7
Data written to SSTDR0
TXI interrupt
Bit
Bit
Bit
Bit
1
6
0
7
generated
SSTDR
SSTDR
Bit
Bit
Bit
7
2
to
to
5
SSTDR0
SSTDR1
(MSB first transmission)
Bit
Bit
Bit
Bit
Bit
6
3
4
7
0
Bit
Bit
Bit
5
4
3
SSTDR0
1 frame
Bit
Bit
Bit
4
5
2
TEI interrupt generated
Bit
Bit
Bit
3
6
1
Bit
Bit
Bit
2
7
0
TEI interrupt
generated
Bit
1
Bit
0