R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 434

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Serial Communication Interface (SCI)
Note:
Rev. 3.00 Mar. 14, 2006 Page 396 of 804
REJ09B0104-0300
Bit
2
1
0
*
Bit Name
TEND
MPB
MPBT
Only 0 can be written, to clear the flag.
Initial
Value
1
0
0
R/W
R
R
R/W
Description
Transmit End
This bit is set to 1 when no error signal is sent from the
receiving side and the next transmit data is ready to be
transferred to TDR.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
Not used in smart card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
When both the TE and ERS bits in SCR are 0
When ERS = 0 and TDRE = 1 after a specified time
passed after completion of 1-byte data transfer. The
set timing depends on the register setting as follows:
When GM = 0 and BLK = 0, 2.5 etu after transmission
start
When GM = 0 and BLK = 1, 1.5 etu after transmission
start
When GM = 1 and BLK = 0, 1.0 etu after transmission
start
When GM = 1 and BLK = 1, 1.0 etu after transmission
start
When 0 is written to TEND after reading TEND = 1
When a TXI interrupt request is issued allowing
DMAC to write the next data to TDR