R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 180

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
Table 7.1
7.2.6
DMDR controls the DMAC operation.
• DMDR_0
Rev. 3.00 Mar. 14, 2006 Page 142 of 804
REJ09B0104-0300
Mode
Repeat transfer
and block transfer
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit after having been read as 1, to clear the flag.
DMA Mode Control Register (DMDR)
Data Access Size, Valid Bits, and Settable Size
DTSZ1
DTF1
DTE
ACT
R/W
R/W
R/W
31
23
15
R
0
0
0
7
0
Data Access Size BKSZH Valid Bits BKSZ Valid Bits
Byte
Word
Longword
DACKE
DTSZ0
DTF0
R/W
R/W
R/W
30
22
—
14
R
0
0
0
6
0
TENDE
MDS1
R/W
R/W
DTA
R/W
29
21
13
—
R
0
0
0
5
0
31 to 16
MDS0
R/W
R/W
28
20
12
—
—
—
R
R
0
0
0
4
0
DREQS
R/(W)*
TSEIE
ERRF
R/W
R/W
27
19
11
—
R
0
0
0
3
0
15 to 0
DMAP2
NRD
R/W
R/W
26
18
—
10
—
R
R
0
0
0
2
0
DMAP1
R/(W)*
ESIE
ESIF
R/W
R/W
25
17
—
Settable Size
(Byte)
1 to 65,536
2 to 131,072
R
4 to 262,144
0
0
9
0
1
0
DMAP0
R/(W)*
DTIF
DTIE
R/W
R/W
24
16
—
R
0
0
8
0
0
0