R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 18

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.5 Interrupt Sources................................................................................................................ 501
13.6 DMAC Interface ................................................................................................................ 502
13.7 CAN Bus Interface............................................................................................................. 503
13.8 Usage Notes ....................................................................................................................... 504
Section 14 Synchronous Serial Communication Unit (SSU) ............................ 509
14.1 Features.............................................................................................................................. 509
14.2 Input/Output Pins............................................................................................................... 511
14.3 Register Descriptions......................................................................................................... 512
14.4 Operation ........................................................................................................................... 526
14.5 Interrupt Requests .............................................................................................................. 545
Rev. 3.00 Mar. 14, 2006 Page xviii of xxxviii
13.4.6 HCAN Halt Mode................................................................................................. 500
13.8.1 Module Stop Mode Setting ................................................................................... 504
13.8.2 Reset ..................................................................................................................... 504
13.8.3 HCAN Sleep Mode............................................................................................... 504
13.8.4 Interrupts............................................................................................................... 505
13.8.5 Error Counters ...................................................................................................... 505
13.8.6 Register Access..................................................................................................... 505
13.8.7 Register Hold in Standby Modes .......................................................................... 505
13.8.8 Use on Bit Manipulation Instructions ................................................................... 505
13.8.9 HCAN TXCR Operation ...................................................................................... 506
13.8.10 HCAN Transmission Setting ................................................................................ 507
13.8.11 Canceling HCAN Reset and HCAN Sleep Mode ................................................. 507
13.8.12 Accessing Mailbox in HCAN Sleep Mode ........................................................... 507
14.3.1 SS Control Register H (SSCRH) .......................................................................... 514
14.3.2 SS Control Register L (SSCRL) ........................................................................... 516
14.3.3 SS Mode Register (SSMR) ................................................................................... 517
14.3.4 SS Enable Register (SSER) .................................................................................. 518
14.3.5 SS Status Register (SSSR).................................................................................... 519
14.3.6 SS Control Register 2 (SSCR2) ............................................................................ 521
14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 523
14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 524
14.3.9 SS Shift Register (SSTRSR)................................................................................. 525
14.4.1 Transfer Clock ...................................................................................................... 526
14.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 526
14.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 527
14.4.4 Communication Modes and Pin Functions ........................................................... 528
14.4.5 SSU Mode............................................................................................................. 530
14.4.6 SCS Pin Control and Conflict Error...................................................................... 538
14.4.7 Clock Synchronous Communication Mode .......................................................... 539