R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 377

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
9.9.5
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 9.48 shows the timing in this case.
9.9.6
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 9.49shows the timing in this case.
Conflict between TCNT Write and Increment Operations
Conflict between TGR Write and Compare Match
Figure 9.48 Conflict between TCNT Write and Increment Operations
P
Address
Write
TCNT input
clock
TCNT
Figure 9.49 Conflict between TGR Write and Compare Match
P
Address
Write
Compare match
signal
TCNT
TGR
TCNT write data
TGR write data
TCNT write cycle
TGR write cycle
N
T1
N
N
address
T1
TCNT
address
TGR
T2
T2
M
N
Rev. 3.00 Mar. 14, 2006 Page 339 of 804
M
Section 9 16-Bit Timer Pulse Unit (TPU)
1
Disabled
REJ09B0104-0300

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