R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 345

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.3
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 9.31 shows the register combinations used in buffer operation.
Table 9.31 Register Combinations in Buffer Operation
• When TGR is an output compare register
Channel
0
3
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 9.13.
Buffer Operation
Buffer register
Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
Figure 9.13 Compare Match Buffer Operation
Compare match signal
Timer general
register
Comparator
Rev. 3.00 Mar. 14, 2006 Page 307 of 804
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
Section 9 16-Bit Timer Pulse Unit (TPU)
TCNT
REJ09B0104-0300