R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 463

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode
Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt
request generated
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted
Start transmission
Figure 12.17 Sample Serial Transmission Flowchart
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
Bit 0
Transfer direction
Bit 1
1 frame
No
No
No
[3]
[2]
[1]
Bit 7
TXI interrupt
request generated
[1] SCI initialization:
[2] SCI state check and transmit data
[3] Serial transmission continuation
Section 12 Serial Communication Interface (SCI)
Bit 0
The TxD pin is automatically
designated as the transmit data output
pin.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0. However, the TDRE
flag is checked and cleared
automatically when the DMAC is
initiated by a transmit data empty
interrupt (TXI) request and writes data
to TDR.
Rev. 3.00 Mar. 14, 2006 Page 425 of 804
Bit 1
TEI interrupt request
generated
Bit 6
Bit 7
REJ09B0104-0300