R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 222

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 7 DMA Controller (DMAC)
B
Address
bus
RD
LHWR
LLWR
TEND
B
Address
bus
RD
LHWR
LLWR
TEND
Rev. 3.00 Mar. 14, 2006 Page 184 of 804
REJ09B0104-0300
(Transfer Destination DDAR = Odd Address and Destination Address Decrement)
Bus
released
Bus
released
Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing
Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing
(Transfer Source DSAR = Odd Address and Source Address Increment)
4m + 1
read cycle
DMA byte
DMA word
read cycle
4m
4m + 2
DMA word
read cycle
DMA word
read cycle
4m + 2
4m + 4
write cycle
read cycle
DMA byte
DMA byte
4n + 5
DMA word
write cycle
DMA word
write cycle
4n + 6
4n
DMA word
write cycle
write cycle
DMA byte
4n + 8
4n +2
Bus
released
Bus
released
read cycle
DMA word
DMA byte
read cycle
4m + 5
4m + 4
DMA word
read cycle
4m + 6
DMA word
read cycle
4m + 6
Last transfer cycle
Last transfer cycle
4m + 8
write cycle
read cycle
DMA byte
DMA byte
4n + 1
DMA word
write cycle
DMA word
write cycle
4n + 4
4n + 2
m and n are integers.
m and n are integers.
DMA word
write cycle
4n + 6
write cycle
4n + 4
DMA byte
released
released
Bus
Bus

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